Logicode is a LeetCode-style platform for Verilog and hardware design. You solve RTL problems in SystemVerilog in a browser editor, simulate against a reference testbench, and synthesize your design to real area and timing numbers. It is built for FPGA, ASIC and RTL design interview prep.

Do I need to install anything?

No. You write code in the browser and we run the simulator and synthesizer for you. There is no toolchain, PDK or license to set up.

How is my solution checked?

A testbench drives the same inputs into your design and our reference, then compares the outputs cycle by cycle. Every run comes back with a waveform, passing or failing, with the reference signals next to yours.

How does the ranking work?

Every accepted design is synthesized, and its area and maximum frequency are compared with every other engineer's on that problem. Your best area and best timing count separately, so you can chase each one. The leaderboard score adds points per problem by difficulty, half for solving it and half for how your results rank.

Which tools do you use?

Simulation runs on Verilator. Synthesis runs on Yosys against the open SkyWater Sky130 PDK. Waveforms open in Surfer.

Why SystemVerilog and not VHDL or Chisel?

SystemVerilog is the language most front-end RTL interviews and teams use. Every problem today is solved in SystemVerilog. We may add other HDLs later.

How is this different from HDLBits?

HDLBits is great for learning the language and stops at functional correctness. Logicode takes a passing design through synthesis, so you also learn what it costs in area and timing and can compete on it.

A core set of problems is free. Premium adds the full problem catalogue and optimized solutions. See the pricing page for current tiers.

SystemVerilog Practice Problems

Browse Logicode's catalog of SystemVerilog and RTL design problems — counters, FSMs, FIFOs, arbiters and more — each solvable in an in-browser editor against a real testbench.

Binary to Thermometer

Easy · Combinational · SystemVerilog

Implement a binary to thermometer decoder module, where the input {din} is an $N$-bit binary word and the output {dout} is the $2^N$-bit thermometer…
Edge Detector

Easy · Sequential · SystemVerilog

Design a module that pulses {dout} one cycle after the rising edge of {din}. A pulse is defined as writing a single-cycle $1$ as shown in the examples…
Sequence Detector

Easy · Sequential · SystemVerilog

Design an overlapping sequence detector for the target sequence 1010. Whenever the target sequence is detected on the serial input stream {din}, {dout}…
Elevator Controller

Medium · Sequential · SystemVerilog

Design an elevator controller FSM with states IDLE, MOVING UP, and MOVING DOWN, reported on {state} as $00$, $01$, and $10$. {up request} is high…
Synchronous FIFO

Medium · Sequential · SystemVerilog

Design a synchronous FIFO storing up to {DEPTH} words of {DATA WIDTH} bits. On each rising edge: a write ({wr en} high, not {full}) stores {wr data} at…
Asynchronous FIFO

Hard · Sequential · SystemVerilog

Design an asynchronous (dual-clock) first-in-first-out buffer that stores up to DEPTH entries of DATA WIDTH bits each, safely transferring data from an…
Thermometer Code Detector

Easy · Combinational · SystemVerilog

Implement a thermometer code detector: assert {isThermometer} when {codeIn} is a valid thermometer code in either orientation — a run of 1s growing from…
Second Largest

Easy · Sequential · SystemVerilog

Design a module that, given a clocked sequence of unsigned values, outputs the second-largest value seen so far in the sequence. If only one value is se…
Vector Sort

Hard · Sequential · SystemVerilog

Design a module that implements the bubble sort algorithm within one cycle. The module takes {din}, an unsigned word; {sortit}, a signal asserted to sta…
Round-Robin Arbiter

Medium · Sequential · SystemVerilog

Design a parameterized round-robin arbiter that grants access to one of N requesters per cycle in a fair, rotating order. The module has N requesters, c…
Register File

Easy · Sequential · SystemVerilog

Design an 8-entry register file of 8-bit words with a single port shared by reads and writes. {wr} is a synchronous write of {din} into entry {addr}, an…
MIPS ALU

Medium · Combinational · SystemVerilog

Design a 32-bit MIPS ALU. Given operands {a} and {b} and a 6-bit operation select code {aluc}, the ALU produces result {r} and the status output {zero}.…
Direct-Mapped Cache

Hard · Sequential · SystemVerilog

Design a direct-mapped write-back cache with a synchronous memory handshake interface. Address Decomposition {cpu addr} is partitioned into two fields:…
Dot Product

Easy · Sequential · SystemVerilog

Implement a module that produces the dot product (scalar product) of two length-$3$ vectors, $A = a 1, a 2, a 3 $ and $B = b 1, b 2, b 3 $. The mo…
Multiply-Accumulate

Medium · Sequential · SystemVerilog

Implement a 2-stage pipelined multiply-accumulate (MAC) unit that multiplies two unsigned operands and adds each product to a running accumulator, with…
FIR Filter

Hard · Sequential · SystemVerilog

Implement a parameterized direct-form FIR (Finite Impulse Response) filter that computes the convolution of the last NUM TAPS input samples with a coeff…
Median Filter

Hard · Sequential · SystemVerilog

Design a streaming sliding-window median filter that accepts one DATA W-bit sample per cycle and outputs the median of the WIN most-recent samples. Shif…
Serial to Parallel Converter

Easy · Sequential · SystemVerilog

Design a serial-to-parallel converter. Each cycle {din valid} is high, one bit is accepted from {din serial}. After $8$ valid bits, the assembled byte…
Parallel to Serial Converter

Easy · Sequential · SystemVerilog

Design a module that takes the input {din} and shifts its LSB to the output {dout} one bit at a time. The module should begin shifting the input’s LSB w…
UART Receiver

Medium · Sequential · SystemVerilog

Design a UART receiver that deserializes the asynchronous serial stream on {rx}, pulsing {rx valid} for one cycle when a valid frame arrives. The bit pe…
LFSR

Medium · Sequential · SystemVerilog

Design a Fibonacci LFSR pseudo-random number generator. A linear feedback shift register (LFSR) is a shift register whose next input bit is the XOR of a…
UART Transmitter

Hard · Sequential · SystemVerilog

Design a UART transmitter that serializes {tx data} onto the {tx} line using the standard asynchronous framing: one start bit, {DATA BITS} data bits (LS…
Fixed Point Adder

Easy · Combinational · SystemVerilog

Implement a parameterized fixed-point adder in sign-magnitude representation. Each operand is {N} bits: bit N-1 is the sign and bits N-2:0 hold the magn…
Square Root

Medium · Combinational · SystemVerilog

Design a module that computes the integer square root of the signed input {in 0}: the largest {out} such that {out}$^2 \le$ {in 0}. If {in 0} is negat…
Fixed Point Multiplier

Medium · Combinational · SystemVerilog

Design a signed fixed-point multiplier. A QM.N fixed-point number is an {M}$+${N}-bit two's-complement integer read with the binary point {N} bits fro…
Modular Exponentiation

Medium · Combinational · SystemVerilog

Write a Verilog module that computes modular exponentiation $y = a^b \mod m$, where {a}, {b}, and {m} are unsigned 4-bit integers and {y} is an unsign…
Galois Field Multiplier

Medium · Combinational · SystemVerilog

Design a combinational module that multiplies two 8-bit elements of $GF(2^8)$ using the AES irreducible polynomial $x^8 + x^4 + x^3 + x + 1$ ($0x11…
Floating Point Multiplier

Hard · Combinational · SystemVerilog

Design a combinational module that multiplies two IEEE 754 single-precision (32-bit) floating-point numbers {a} and {b} and produces their product {resu…
Fibonacci Generator

Easy · Sequential · SystemVerilog

Design a module that generates the Fibonacci sequence starting with 1 and 1 as the first two numbers. The Fibonacci sequence is a sequence of numbers wh…
Binary to BCD

Medium · Sequential · SystemVerilog

Design a sequential module that converts an unsigned binary number to its Binary Coded Decimal (BCD) representation. Conversion is triggered by assertin…
Clock Divider

Easy · Sequential · SystemVerilog

Design a module that, from the input clock, generates three output clocks with $2\times$, $4\times$, and $6\times$ its period. While {resetn} is a…
Fractional Clock Divider

Easy · Sequential · SystemVerilog

Design a fractional frequency divider that produces {clk div} at $1/($ {MUL2 DIV CLK} $/2)$ of the {clk} frequency — half-integer ratios like $3.5$…
PWM Controller

Medium · Sequential · SystemVerilog

Design a PWM controller that produces complementary high-side ({pwm h}) and low-side ({pwm l}) gate-drive outputs with a programmable dead-time gap betw…
Stopwatch

Easy · Sequential · SystemVerilog

Design a stopwatch that counts hours, minutes, and seconds. {Secs} increments on each rising edge of {CLK} and wraps from $59$ to $0$. {Mins} increm…
Rate Limiter

Medium · Sequential · SystemVerilog

Design a token bucket rate limiter. The bucket holds at most {BUCKET DEPTH} tokens and starts full after reset. Each rising edge applies refill, then co…
Carry Look-Ahead Adder

Medium · Combinational · SystemVerilog

Design a parameterized carry look-ahead adder that also exposes its generate, propagate, and carry signals. {cout} and {sum} together form the (N+1)-bit…
Prefix Sum

Medium · Combinational · SystemVerilog

Design a parallel prefix sum module. A prefix sum, or scan, gives for every element of a sequence the total of the elements up to and including it. Comp…
Priority Encoder

Medium · Combinational · SystemVerilog

Design a combinational module that simultaneously finds the three highest-priority set bits in a 16-bit request vector and reports them via a grant vect…
Divisible by 3

Easy · Sequential · SystemVerilog

Design a circuit that determines whether an input value is evenly divisible by three. The input value is of unknown length and is left-shifted one bit a…
SPI Master

Medium · Sequential · SystemVerilog

Design a synchronous SPI Mode-0 master that performs a full-duplex 8-bit transfer: shifting {tx data} out on {mosi} while simultaneously capturing 8 bit…
Skid Buffer

Medium · Sequential · SystemVerilog

Design a valid/ready skid buffer (a full register slice): an output register plus exactly one slot of skid storage, so that every output and {s ready} c…
Hamming Decoder

Easy · Combinational · SystemVerilog

Implement a Hamming(7,4) syndrome decoder that accepts a 7-bit encoded codeword, computes the 3-bit syndrome to detect and correct any single-bit error…
Ping-Pong Buffer

Medium · Sequential · SystemVerilog

Design a ping-pong (double-buffer) controller that manages two fixed-depth storage banks, keeping one bank accepting writes while the other is drained b…
Reciprocal

Hard · Sequential · SystemVerilog

Compute the reciprocal $1/d$ of an unsigned fixed-point divisor using the iterative Newton-Raphson method, producing a result in the same Q(WIDTH-FRAC…

SystemVerilog Practice Problems

Binary to Thermometer

Edge Detector

Sequence Detector

Elevator Controller

Synchronous FIFO

Asynchronous FIFO

Thermometer Code Detector

Second Largest

Vector Sort

Round-Robin Arbiter

Register File

MIPS ALU

Direct-Mapped Cache

Dot Product

Multiply-Accumulate

FIR Filter

Median Filter

Serial to Parallel Converter

Parallel to Serial Converter

UART Receiver

LFSR

UART Transmitter

Fixed Point Adder

Square Root

Fixed Point Multiplier

Modular Exponentiation

Galois Field Multiplier

Floating Point Multiplier

Fibonacci Generator

Binary to BCD

Clock Divider

Fractional Clock Divider

PWM Controller

Stopwatch

Rate Limiter

Carry Look-Ahead Adder

Prefix Sum

Priority Encoder

Divisible by 3

SPI Master

Skid Buffer

Hamming Decoder

Ping-Pong Buffer

Reciprocal