SystemVerilog Practice Problems

Browse Logicode's catalog of SystemVerilog and RTL design problems — counters, FSMs, FIFOs, arbiters and more — each solvable in an in-browser editor against a real testbench.

• Counter

  Easy · Sequential · SystemVerilog

  Build a module which controls a counter. The counter starts counting when the start button (start) is pressed (pulses) and increases by 1 every clock cy…

• Binary to Thermometer Decoder

  Easy · Combinational · SystemVerilog

  Thermometer (a.k.a. unary) coding is frequently used in digital systems applications to represent a natural number. In a thermometer code, a binary numb…

• Polynomial 1

  Easy · Combinational · SystemVerilog

  Design a module that computes {y} as {x}^2 $+$ 2{x} $+$ 1.

• Fizzbuzz

  Easy · Sequential · SystemVerilog

  Design a module that counts incrementally every clock cycle and determines whether or not the counter value is evenly divisible by parameters {FIZZ}, {B…

• Basic ALU

  Easy · Combinational · SystemVerilog

  Design a module that acts as an Arithmetic Logic Unit (ALU) and performs a set of operations on input operands {a} and {b}. The outputs of each operatio…

• Sequence Detector

  Easy · Sequential · SystemVerilog

  Design a module that, given a stream of input bits, pulses a $1$ on the output {dout} whenever a $b1010$ sequence is detected on the input {din}. Wh…

• Dot Product

  Easy · Sequential · SystemVerilog

  Implement a module that produces the dot product (scalar product) of two length-$3$ vectors, A = a1, a2, a3 and B = b1, b2, b3 . The module has one po…

• One Hot Encoding Detector

  Easy · Combinational · SystemVerilog

  Design a module that outputs $1$ if the input {din} is a one-hot value, and outputs $0$ otherwise. One-hot values have a single bit that is a $1$…

• Bubble Sort

  Hard · Sequential · SystemVerilog

  Design a module that implements the bubble sort algorithm within one cycle. The module takes {din}, an unsigned word; {sortit}, a signal asserted to sta…

• Thermometer Code Detector

  Medium · Combinational · SystemVerilog

  Thermometer (a.k.a. unary) coding is frequently used in digital systems applications to represent a natural number. In a thermometer code, a binary numb…

• Elevator Controller

  Medium · Sequential · SystemVerilog

  Design a Verilog module for a simple elevator controller FSM with states IDLE, MOVING UP, and MOVING DOWN. The elevator transitions between states based…

• Modular Exponentiation

  Hard · Combinational · SystemVerilog

  Write a Verilog module that computes modular exponentiation $y = a^b \mod m$, where {a}, {b}, and {m} are unsigned 4-bit integers and {y} is an unsign…

• Polynomial 5

  Easy · Combinational · SystemVerilog

  Design a module that computes {y} as ({a} $+$ {b})$^2$ $-$ ({a} $-$ {b})$^2$.

• Piso Shift Register

  Medium · Sequential · SystemVerilog

  Design a module that takes the multi-bit input {din} and shifts the input value’s least significant bit (rightmost bit) to the single-bit output {dout}…

• FIR Filter

  Hard · Sequential · SystemVerilog

  Implement a parameterized direct-form FIR (Finite Impulse Response) filter that computes the convolution of the last NUM TAPS input samples with a stati…

• Round-Robin Arbiter

  Medium · Sequential · SystemVerilog

  Design a parameterized round-robin arbiter that grants access to one of N requesters per cycle in a fair, rotating order. The module has N requesters, c…

• SPI Master

  Medium · Sequential · SystemVerilog

  Design a synchronous SPI Mode-0 master that performs a full-duplex 8-bit transfer: shifting {tx data} out on {mosi} while simultaneously capturing 8 bit…

• Skid Buffer

  Medium · Sequential · SystemVerilog

  Design a valid/ready elastic buffer with exactly one slot of skid storage that decouples the upstream and downstream ready timing paths. The module uses…

• Pipelined Multiply-Accumulate (MAC) Unit

  Hard · Sequential · SystemVerilog

  Implement a 2-stage pipelined multiply-accumulate (MAC) unit that multiplies two unsigned operands and adds each product to a running accumulator, with…

• IIR Biquad Filter (Direct Form II Transposed)

  Hard · Sequential · SystemVerilog

  Implement a second-order IIR biquad filter in Direct Form II Transposed. The filter realizes the transfer function: $H(z) = \frac{b0 + b1 \cdot z^{-1}…

• Sliding Window Median Filter

  Hard · Sequential · SystemVerilog

  Design a streaming sliding-window median filter that accepts one DATA W-bit sample per cycle and outputs the median of the WIN most-recent samples. Shif…

• Direct-Mapped Write-Back Cache

  Hard · Sequential · SystemVerilog

  Design a direct-mapped write-back cache with a synchronous memory handshake interface. Address Decomposition {cpu addr} is partitioned into two fields:…

• Fibonacci Generator

  Easy · Sequential · SystemVerilog

  Design a module that generates the Fibonacci sequence starting with 1 and 1 as the first two numbers. The Fibonacci sequence is a sequence of numbers wh…

• Divisble by 5

  Medium · Sequential · SystemVerilog

  Design a module that determines whether an input value is evenly divisible by five. The input value is of unknown length and is left-shifted one bit at…

• MIPS ALU

  Medium · Combinational · SystemVerilog

  Design a 32-bit MIPS ALU. Given operands {a} and {b} and a 6-bit operation select code {aluc}, the ALU produces result {r} and the status output {zero}.…

• IEEE 754 Single-Precision Floating-Point Multiplier

  Hard · Combinational · SystemVerilog

  Design a combinational module that multiplies two IEEE 754 single-precision (32-bit) floating-point numbers {a} and {b} and produces their product {resu…

• Fibonacci

  Medium · Combinational · SystemVerilog

  Implement a Verilog module that computes the Fibonacci value for a signed index {in 0} and outputs a signed result {out}. If {in 0} $\le$ 0, {out} is…

• Asynchronous FIFO (Dual-Clock)

  Hard · Sequential · SystemVerilog

  Design an asynchronous (dual-clock) first-in-first-out buffer that stores up to DEPTH entries of DATA WIDTH bits each, safely transferring data from an…

• Gradient Descent

  Hard · Sequential · SystemVerilog

  Design a module that performs one step of gradient descent weight update. On each rising edge of {clk}, if {rst} is asserted, {updated weight} resets to…

• Logarithm Base 2

  Medium · Combinational · SystemVerilog

  Write a Verilog module to compute the integer logarithm base 2 of {in 0}, where {in 0} is a signed integer and {out} is a signed integer. If {in 0} $\l…

• AXI4-Lite Slave Register File

  Hard · Sequential · SystemVerilog

  Design an AXI4-Lite subordinate (slave) controller that exposes a small register file over the AXI4-Lite bus. AXI4-Lite Overview AXI4-Lite defines five…

• Edge Detector

  Easy · Sequential · SystemVerilog

  Design a module that pulses {dout} one cycle after the rising edge of {din}. A pulse is defined as writing a single-cycle $1$ as shown in the examples…

• Divisible by 3

  Medium · Sequential · SystemVerilog

  Design a circuit that determines whether an input value is evenly divisible by three. The input value is of unknown length and is left-shifted one bit a…

• Galois Field GF(2^8) Multiplier

  Hard · Combinational · SystemVerilog

  Design a combinational module that multiplies two 8-bit elements of $GF(2^8)$ using the AES irreducible polynomial $x^8 + x^4 + x^3 + x + 1$ ($0x11…

• Barrel Shifter

  Easy · Combinational · SystemVerilog

  Design a module that can perform right shifts by variable amounts. The barrel shifter takes an input word {in} and a control signal {ctrl} that specifie…

• Fractional Frequency Divider

  Easy · Sequential · SystemVerilog

  Design a fractional frequency divider that produces {clk div} at exactly $ 1 / ( $ {MUL2 DIV CLK} $ / 2) $ of the {clk} frequency. The module uses a…

• Non-Restoring Integer Divider

  Medium · Sequential · SystemVerilog

  Implement a non-restoring unsigned integer divider that computes the quotient and remainder of two $N$-bit inputs over $N$ clock cycles using an ite…

• Parallel Prefix Leading-One Detector

  Medium · Combinational · SystemVerilog

  Design a combinational module that simultaneously finds the three highest-priority set bits in a 16-bit request vector and reports them via a grant vect…

• Register File

  Medium · Sequential · SystemVerilog

  Design a simple 1-read/write (1RW) register file (RF) using a multidimensional array of flip-flops in Verilog. The RF has $8$ entries, each storing on…

• Booth Radix-2 Multiplier

  Hard · Sequential · SystemVerilog

  Implement a Booth Radix-2 iterative multiplier that computes the signed two's complement product of two $N$-bit inputs over $N+1$ clock cycles. Hand…

• UART Receiver

  Medium · Sequential · SystemVerilog

  Design a UART receiver that deserializes an asynchronous serial bitstream on {rx} into parallel data on {rx data}, asserting {rx valid} for one cycle wh…

• Gray Code to Binary Conversion

  Easy · Combinational · SystemVerilog

  Given a Gray code value {gray}, output its corresponding binary index {bin}. The input {gray} is interpreted as a standard Gray code value. The output {…

• Polynomial 6

  Easy · Combinational · SystemVerilog

  Design a purely combinational Verilog module that evaluates the quadratic polynomial $y = a2 x^2 + a1 x + a0$ using signed two's-complement arithmetic…

• Second Largest

  Easy · Sequential · SystemVerilog

  Design a module that, given a clocked sequence of unsigned values, outputs the second-largest value seen so far in the sequence. If only one value is se…

• CRC-16/CCITT Generator

  Hard · Sequential · SystemVerilog

  Design a byte-serial CRC-16/CCITT generator that processes one byte per clock cycle, accumulates a running CRC over a frame of arbitrary length, and ass…

• Newton-Raphson Reciprocal

  Hard · Sequential · SystemVerilog

  Compute the reciprocal $1/d$ of an unsigned fixed-point divisor using the iterative Newton-Raphson method, producing a result in the same Q(WIDTH-FRAC…

• Token Bucket Rate Limiter

  Medium · Sequential · SystemVerilog

  Design a parameterized token bucket rate limiter that tracks a saturating token counter and grants multi-token burst requests only up to the tokens avai…

• IEEE 754 to Q16.16 Fixed-Point Converter

  Hard · Combinational · SystemVerilog

  Design a combinational module that converts a 32-bit IEEE 754 single-precision floating-point value {float in} into a 32-bit signed Q16.16 fixed-point v…

• Hamming(7,4) Syndrome Decoder with SEC

  Hard · Combinational · SystemVerilog

  Implement a Hamming(7,4) syndrome decoder that accepts a 7-bit encoded codeword, computes the 3-bit syndrome to detect and correct any single-bit error…

• Parallel CRC-32

  Hard · Combinational · SystemVerilog

  Design a purely combinational module that computes the CRC-32/ISO-HDLC checksum update in one cycle: given an input data word {data in} and the current…

• Carry-Save Adder (3:2 Compressor)

  Hard · Combinational · SystemVerilog

  Implement a parameterized combinational carry-save adder (CSA) 3:2 compressor that reduces three N-bit unsigned operands to two N-bit carry-save outputs…

• Parallel Prefix Sum (Inclusive Scan)

  Medium · Combinational · SystemVerilog

  Design a purely combinational module that computes the inclusive prefix sum (also called an inclusive scan) of $N$ packed $W$-bit unsigned integers.…

• Ping-Pong Buffer Controller

  Medium · Sequential · SystemVerilog

  Design a ping-pong (double-buffer) controller that manages two fixed-depth storage banks, keeping one bank accepting writes while the other is drained b…

• Square Root

  Medium · Combinational · SystemVerilog

  Write a Verilog module to compute the integer square root of {in 0}, where {in 0} is a signed integer and {out} is a signed integer. If {in 0} is negati…

• Stopwatch

  Medium · Sequential · SystemVerilog

  Design a stopwatch module that counts hours, minutes, and seconds. {Secs} counts from $0$ to $59$, incrementing by $1$ on each rising edge of {CLK…

• Synchronous FIFO

  Medium · Sequential · SystemVerilog

  Design a synchronous first-in-first-out (FIFO) buffer that stores up to DEPTH entries of DATA WIDTH bits each, operating in a single clock domain. The F…

• Rotate Left

  Easy · Combinational · SystemVerilog

  Design a module that performs a circular left rotation on an 8-bit input {in} by a variable amount {shift}. The rotation amount ranges from $0$ to $7…

• Divide by Evens Clock Generator

  Easy · Sequential · SystemVerilog

  Design a module that, given an input clock signal, generates three output clock signals with $2x$, $4x$, and $6x$ the period of the input clock. W…

• Fixed Point Adder

  Easy · Combinational · SystemVerilog

  Implement a parameterized fixed-point adder that operates in sign-magnitude representation. Each operand is {N} bits wide: the most significant bit (bit…

• Serial to Parallel Converter

  Easy · Sequential · SystemVerilog

  Design a serial-to-parallel converter module. The module accepts one bit of input data per cycle on {din serial} when {din valid} is high. After receivi…

• I2C Master Controller

  Hard · Sequential · SystemVerilog

  Design a single-byte I2C master controller that generates START and STOP conditions, clocks an address byte and a data byte over the open-drain {scl o}/…

• LFSR Pseudo-Random Number Generator

  Medium · Sequential · SystemVerilog

  Implement a Fibonacci LFSR (Linear Feedback Shift Register) pseudo-random number generator that shifts right on each enabled clock cycle, producing a ma…

• Fixed-Point Multiplier (Q-Format)

  Medium · Combinational · SystemVerilog

  Design a purely combinational signed fixed-point multiplier in Q-format (QM.N) that multiplies two signed inputs and returns a result in the same format…

• Majority

  Easy · Combinational · SystemVerilog

  Design a module that computes the majority function of three inputs {a}, {b}, and {c}. The output {out} should be $1$ if at least two inputs are $1$…

• Binary to BCD Converter (Double Dabble)

  Medium · Sequential · SystemVerilog

  Design a sequential module that converts a DATA WIDTH-bit unsigned binary number to its Binary Coded Decimal (BCD) representation using the Double Dabbl…

• MSE Loss

  Hard · Sequential · SystemVerilog

  Design a module that computes the mean squared error (MSE) between two 4-element signed integer vectors. The MSE is defined as the average of the four s…

• Carry Look-Ahead Adder

  Medium · Combinational · SystemVerilog

  Design a parameterized N-bit carry look-ahead adder that exposes the full carry-chain intermediate signals as output ports. Primary outputs {sum} is the…

• Comparator Operations

  Easy · Combinational · SystemVerilog

  Design a module that performs an unsigned magnitude comparison of two input values {a} and {b} and outputs whether the first input is {greater} than the…

• UART Transmitter

  Hard · Sequential · SystemVerilog

  Design a UART transmitter that serializes {tx data} onto the {tx} line using the standard asynchronous framing: one start bit, {DATA BITS} data bits (LS…

• Conditional Adder

  Easy · Combinational · SystemVerilog

  Design a module for Conditional Addition. The module performs conditional addition based on the value of {s}. The output {Z} is determined by adding pai…

• Multiplier Select

  Easy · Sequential · SystemVerilog

  Design a multiplier module that can perform multiplication operations on two different pairs of operands ({a1}$×${b1} or {a2}$×${b2}) based on a sel…

• Counting Ones

  Easy · Combinational · SystemVerilog

  Design a module that, given an input value {din}, outputs the number of bits that are equal to $1$ on {dout}.

• CORDIC Sin/Cos

  Hard · Sequential · SystemVerilog

  Compute the sine and cosine of an input angle using the iterative CORDIC (COordinate Rotation DIgital Computer) rotation-mode algorithm in signed fixed-…

• Parameterized PWM Controller with Dead-Time Insertion

  Medium · Sequential · SystemVerilog

  Design a PWM controller that produces complementary high-side ({pwm h}) and low-side ({pwm l}) gate-drive outputs with a programmable dead-time gap betw…

• Trailing Zeros

  Easy · Combinational · SystemVerilog

  Find the number of trailing 0s in the binary representation of the input {din}. If the input value is all 0s, the number of trailing 0s is the data widt…

• Maximum Finder

  Medium · Sequential · SystemVerilog

  Implement a 2-stage pipelined module that finds the maximum of four unsigned inputs {x0}, {x1}, {x2}, and {x3}. On each rising edge of {clk}, the first…

• 8b/10b Line Encoder

  Hard · Sequential · SystemVerilog

  Design a pipelined 8b/10b line encoder that converts each 8-bit input symbol into a 10-bit encoded output while maintaining DC balance through a running…