SystemVerilog Practice Problems

Browse Logicode's catalog of SystemVerilog and RTL design problems — counters, FSMs, FIFOs, arbiters and more — each solvable in an in-browser editor against a real testbench.

• Counter

  Easy · Sequential · SystemVerilog

  Design a module that controls a counter. Pulsing {start} makes {count} increase by 1 every clock cycle; pulsing {stop} halts it. Pulsing {reset} clears…

• Binary to Thermometer Decoder

  Easy · Combinational · SystemVerilog

  Implement a binary to thermometer decoder module, where the input {din} is an $N$-bit binary word and the output {dout} is the $2^N$-bit thermometer…

• Polynomial 1

  Easy · Combinational · SystemVerilog

  Design a module that computes {y} as {x}$^2$ $+ 2${x} $+ 1$.

• Fizzbuzz

  Easy · Sequential · SystemVerilog

  Design a module with an internal counter that increments every clock cycle while {resetn} is deasserted, counting from $0$ and restarting when {MAX CY…

• Sequence Detector

  Easy · Sequential · SystemVerilog

  Design a module that, given a stream of input bits, pulses a $1$ on the output {dout} whenever a 1010 sequence is detected on the input {din}. If two…

• Basic ALU

  Easy · Combinational · SystemVerilog

  Design a module that acts as a simplified Arithmetic Logic Unit (ALU): instead of selecting one operation with an opcode, it computes every operation on…

• One Hot Encoding Detector

  Easy · Combinational · SystemVerilog

  Design a module that outputs $1$ if the input {din} is a one-hot value, and outputs $0$ otherwise. One-hot values have a single bit that is a $1$…

• Dot Product

  Easy · Sequential · SystemVerilog

  Implement a module that produces the dot product (scalar product) of two length-$3$ vectors, $A = a 1, a 2, a 3 $ and $B = b 1, b 2, b 3 $. The mo…

• Thermometer Code Detector

  Medium · Combinational · SystemVerilog

  Thermometer (a.k.a. unary) coding is frequently used in digital systems applications to represent a natural number. In a thermometer code, a binary numb…

• Bubble Sort

  Hard · Sequential · SystemVerilog

  Design a module that implements the bubble sort algorithm within one cycle. The module takes {din}, an unsigned word; {sortit}, a signal asserted to sta…

• Modular Exponentiation

  Hard · Combinational · SystemVerilog

  Write a Verilog module that computes modular exponentiation $y = a^b \mod m$, where {a}, {b}, and {m} are unsigned 4-bit integers and {y} is an unsign…

• Elevator Controller

  Medium · Sequential · SystemVerilog

  Design a Verilog module for a simple elevator controller FSM with states IDLE, MOVING UP, and MOVING DOWN. The elevator transitions between states based…

• Polynomial 5

  Easy · Combinational · SystemVerilog

  Design a module that computes {y} as ({a} $+$ {b})$^2$ $-$ ({a} $-$ {b})$^2$.

• Piso Shift Register

  Medium · Sequential · SystemVerilog

  Design a module that takes the input {din} and shifts its LSB to the output {dout} one bit at a time. The module should begin shifting the input’s LSB w…

• FIR Filter

  Hard · Sequential · SystemVerilog

  Implement a parameterized direct-form FIR (Finite Impulse Response) filter that computes the convolution of the last NUM TAPS input samples with a stati…

• Round-Robin Arbiter

  Medium · Sequential · SystemVerilog

  Design a parameterized round-robin arbiter that grants access to one of N requesters per cycle in a fair, rotating order. The module has N requesters, c…

• SPI Master

  Medium · Sequential · SystemVerilog

  Design a synchronous SPI Mode-0 master that performs a full-duplex 8-bit transfer: shifting {tx data} out on {mosi} while simultaneously capturing 8 bit…

• Skid Buffer

  Medium · Sequential · SystemVerilog

  Design a valid/ready elastic buffer with exactly one slot of skid storage that decouples the upstream and downstream ready timing paths. The module uses…

• Pipelined Multiply-Accumulate (MAC) Unit

  Hard · Sequential · SystemVerilog

  Implement a 2-stage pipelined multiply-accumulate (MAC) unit that multiplies two unsigned operands and adds each product to a running accumulator, with…

• Sliding Window Median Filter

  Hard · Sequential · SystemVerilog

  Design a streaming sliding-window median filter that accepts one DATA W-bit sample per cycle and outputs the median of the WIN most-recent samples. Shif…

• Direct-Mapped Write-Back Cache

  Hard · Sequential · SystemVerilog

  Design a direct-mapped write-back cache with a synchronous memory handshake interface. Address Decomposition {cpu addr} is partitioned into two fields:…

• Second Largest

  Easy · Sequential · SystemVerilog

  Design a module that, given a clocked sequence of unsigned values, outputs the second-largest value seen so far in the sequence. If only one value is se…

• Gray Code to Binary Conversion

  Easy · Combinational · SystemVerilog

  Design a module that converts the Gray code value {gray} to its corresponding binary value {bin}.

• Ping-Pong Buffer Controller

  Medium · Sequential · SystemVerilog

  Design a ping-pong (double-buffer) controller that manages two fixed-depth storage banks, keeping one bank accepting writes while the other is drained b…

• Rotate Left

  Easy · Combinational · SystemVerilog

  Design a module that circularly rotates {in} left by {shift} positions: bits shifted out of the most-significant end wrap around into the least-signific…

• Fixed-Point Multiplier (Q-Format)

  Medium · Combinational · SystemVerilog

  Design a purely combinational signed fixed-point multiplier in Q-format (QM.N) that multiplies two signed inputs and returns a result in the same format…

• IEEE 754 Single-Precision Floating-Point Multiplier

  Hard · Combinational · SystemVerilog

  Design a combinational module that multiplies two IEEE 754 single-precision (32-bit) floating-point numbers {a} and {b} and produces their product {resu…

• Asynchronous FIFO (Dual-Clock)

  Hard · Sequential · SystemVerilog

  Design an asynchronous (dual-clock) first-in-first-out buffer that stores up to DEPTH entries of DATA WIDTH bits each, safely transferring data from an…

• Gradient Descent

  Hard · Sequential · SystemVerilog

  Design a module that performs one step of gradient descent weight update. On each rising edge of {clk}, if {rst} is asserted, {updated weight} resets to…

• Synchronous FIFO

  Medium · Sequential · SystemVerilog

  Design a synchronous first-in-first-out (FIFO) buffer that stores up to DEPTH entries of DATA WIDTH bits each, operating in a single clock domain. The F…

• Serial to Parallel Converter

  Easy · Sequential · SystemVerilog

  Design a serial-to-parallel converter. Each cycle {din valid} is high, one bit is accepted from {din serial}. After $8$ valid bits, the assembled byte…

• LFSR Pseudo-Random Number Generator

  Medium · Sequential · SystemVerilog

  Implement a Fibonacci LFSR (Linear Feedback Shift Register) pseudo-random number generator that shifts right on each enabled clock cycle, producing a ma…

• Galois Field GF(2^8) Multiplier

  Hard · Combinational · SystemVerilog

  Design a combinational module that multiplies two 8-bit elements of $GF(2^8)$ using the AES irreducible polynomial $x^8 + x^4 + x^3 + x + 1$ ($0x11…

• Edge Detector

  Easy · Sequential · SystemVerilog

  Design a module that pulses {dout} one cycle after the rising edge of {din}. A pulse is defined as writing a single-cycle $1$ as shown in the examples…

• Fibonacci Generator

  Easy · Sequential · SystemVerilog

  Design a module that generates the Fibonacci sequence starting with 1 and 1 as the first two numbers. The Fibonacci sequence is a sequence of numbers wh…

• Divisble by 5

  Medium · Sequential · SystemVerilog

  Design a module that determines whether an input value is evenly divisible by five. The input value is of unknown length and is left-shifted one bit at…

• Maximum Finder

  Medium · Sequential · SystemVerilog

  Implement a 2-stage pipelined module that finds the maximum of four unsigned inputs {x0}, {x1}, {x2}, and {x3}. On each rising edge of {clk}, the first…

• MIPS ALU

  Medium · Combinational · SystemVerilog

  Design a 32-bit MIPS ALU. Given operands {a} and {b} and a 6-bit operation select code {aluc}, the ALU produces result {r} and the status output {zero}.…

• Fractional Frequency Divider

  Easy · Sequential · SystemVerilog

  Design a fractional frequency divider that produces {clk div} at $1/($ {MUL2 DIV CLK} $/2)$ of the {clk} frequency — half-integer ratios like $3.5$…

• Divisible by 3

  Medium · Sequential · SystemVerilog

  Design a circuit that determines whether an input value is evenly divisible by three. The input value is of unknown length and is left-shifted one bit a…

• Square Root

  Medium · Combinational · SystemVerilog

  Write a Verilog module to compute the integer square root of {in 0}, where {in 0} is a signed integer and {out} is a signed integer. If {in 0} is negati…

• Fibonacci

  Medium · Combinational · SystemVerilog

  Implement a Verilog module that computes the Fibonacci value for a signed index {in 0} and outputs a signed result {out}. If {in 0} $\le$ 0, {out} is…

• Parallel Prefix Leading-One Detector

  Medium · Combinational · SystemVerilog

  Design a combinational module that simultaneously finds the three highest-priority set bits in a 16-bit request vector and reports them via a grant vect…

• Divide by Evens Clock Generator

  Easy · Sequential · SystemVerilog

  Design a module that, from the input clock, generates three output clocks with $2\times$, $4\times$, and $6\times$ its period. While {resetn} is a…

• Logarithm Base 2

  Medium · Combinational · SystemVerilog

  Write a Verilog module to compute the integer logarithm base 2 of {in 0}, where {in 0} is a signed integer and {out} is a signed integer. If {in 0} $\l…

• Register File

  Medium · Sequential · SystemVerilog

  Design a simple 1-read/write (1RW) register file (RF) using a multidimensional array of flip-flops in Verilog. The RF has $8$ entries, each storing on…

• Carry Look-Ahead Adder

  Medium · Combinational · SystemVerilog

  Design a parameterized N-bit carry look-ahead adder that exposes the full carry-chain intermediate signals as output ports. {sum} is the N-bit result of…

• UART Receiver

  Medium · Sequential · SystemVerilog

  Design a UART receiver that deserializes an asynchronous serial bitstream on {rx} into parallel data on {rx data}, asserting {rx valid} for one cycle wh…

• Parameterized PWM Controller with Dead-Time Insertion

  Medium · Sequential · SystemVerilog

  Design a PWM controller that produces complementary high-side ({pwm h}) and low-side ({pwm l}) gate-drive outputs with a programmable dead-time gap betw…

• Counting Ones

  Easy · Combinational · SystemVerilog

  Design a module that, given an input value {din}, outputs the number of bits that are equal to $1$ on {dout}.

• Fixed Point Adder

  Easy · Combinational · SystemVerilog

  Implement a parameterized fixed-point adder in sign-magnitude representation. Each operand is {N} bits: bit N-1 is the sign and bits N-2:0 hold the magn…

• Hamming(7,4) Syndrome Decoder with SEC

  Hard · Combinational · SystemVerilog

  Implement a Hamming(7,4) syndrome decoder that accepts a 7-bit encoded codeword, computes the 3-bit syndrome to detect and correct any single-bit error…

• Token Bucket Rate Limiter

  Medium · Sequential · SystemVerilog

  Design a parameterized token bucket rate limiter that tracks a saturating token counter and grants multi-token burst requests only up to the tokens avai…

• Newton-Raphson Reciprocal

  Hard · Sequential · SystemVerilog

  Compute the reciprocal $1/d$ of an unsigned fixed-point divisor using the iterative Newton-Raphson method, producing a result in the same Q(WIDTH-FRAC…

• Polynomial 6

  Easy · Combinational · SystemVerilog

  Design a purely combinational module that evaluates the quadratic polynomial $y = a 2 x^2 + a 1 x + a 0$ in signed two's-complement arithmetic. All op…

• Trailing Zeros

  Easy · Combinational · SystemVerilog

  Design a model that detects the number of trailing 0s in the binary representation of the input {din}. If the input value is all 0s, the number of trail…

• Carry-Save Adder (3:2 Compressor)

  Hard · Combinational · SystemVerilog

  Implement a parameterized combinational carry-save adder (CSA) 3:2 compressor that reduces three N-bit unsigned operands to two N-bit carry-save outputs…

• Parallel Prefix Sum (Inclusive Scan)

  Medium · Combinational · SystemVerilog

  Design a purely combinational module that computes the inclusive prefix sum (also called an inclusive scan) of $N$ packed $W$-bit unsigned integers.…

• Stopwatch

  Medium · Sequential · SystemVerilog

  Design a stopwatch module that counts hours, minutes, and seconds. {Secs} counts from $0$ to $59$, incrementing by $1$ on each rising edge of {CLK…

• UART Transmitter

  Hard · Sequential · SystemVerilog

  Design a UART transmitter that serializes {tx data} onto the {tx} line using the standard asynchronous framing: one start bit, {DATA BITS} data bits (LS…

• MSE Loss

  Hard · Sequential · SystemVerilog

  Design a module that computes the mean squared error (MSE) between two 4-element signed integer vectors. The MSE is defined as the average of the four s…

• Binary to BCD Converter (Double Dabble)

  Medium · Sequential · SystemVerilog

  Design a sequential module that converts an unsigned binary number to its Binary Coded Decimal (BCD) representation. Conversion is triggered by assertin…