Fractional Frequency Divider
Easy · Sequential · SystemVerilog
Design a fractional frequency divider that produces {clk_div} at $1/($ {MUL2_DIV_CLK} $/2)$ of the {clk} frequency — half-integer ratios like $3.5$.
Because the ratio is fractional, {clk_div} uses both edges of {clk}: each output period spans {MUL2_DIV_CLK} half-periods of the input clock, with edges landing on half-cycle boundaries so every output period is uniform. The exact waveform is shown in the examples below.
When {rst_n} is low, all internal state clears asynchronously and {clk_div} is forced low.