Fractional Clock Divider
Easy · Sequential · SystemVerilog · VHDL
Design a fractional clock divider that divides clk by MUL2_DIV_CLK/2, a half-integer ratio such as 3.5 for the default MUL2_DIV_CLK = 7.
clk_div has a period of MUL2_DIV_CLK half-cycles of clk, so its edges fall on both rising and falling edges of clk. Each period begins with clk_div rising; it stays high for three half-cycles of clk and is low for the rest of the period. The first period begins at the first rising edge of clk after reset.
rst_n is an asynchronous, active-low reset that holds clk_div low.