Asynchronous FIFO (Dual-Clock)
Hard · Sequential · SystemVerilog
Design an asynchronous (dual-clock) first-in-first-out buffer that stores up to DEPTH entries of DATA_WIDTH bits each, safely transferring data from an independent write clock domain to an independent read clock domain.
The FIFO has two completely separate clock domains. All write-side operations are synchronous to the rising edge of {wr_clk}. All read-side operations are synchronous to the rising edge of {rd_clk}. The two clocks may run at different frequencies and have no phase relationship.
**Write domain**
On each rising edge of {wr_clk}:
- If {wr_en} is asserted and the FIFO is not full, {wr_data} is written to the tail of the FIFO and the write pointer advances. - If {wr_en} is asserted but {wr_full} is already asserted, the write is silently discarded — no data is corrupted and the write pointer does not advance.
{wr_rst_n} is an asynchronous active-low reset for the write domain. When {wr_rst_n} is driven low, the write pointer and {wr_full} reset immediately, without waiting for a clock edge.