Sequence Detector
Easy · Sequential · SystemVerilog · VHDL
Design an overlapping sequence detector for the target sequence 1010.
Whenever the target sequence is detected on the serial input stream din, dout should pulse high the following cycle. Sequences may overlap, so the stream 101010 completes two sequences.
resetn is a synchronous, active-low reset; it discards the bits received so far and clears dout.