UART Transmitter
Hard · Sequential · SystemVerilog
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Design a UART transmitter.
A UART sends words over a single wire with no clock beside it. The line idles high, and each word goes out as a frame: a low start bit, the data bits, an optional parity bit and one or more high stop bits, each held for one bit period. Sender and receiver agree on the bit period in advance, and the receiver times the rest of the frame from the moment the line goes low.
The bit period is ⌊CLK_FREQ / BAUD_RATE⌋ cycles. A frame on tx is a start bit of 0; the DATA_BITS bits of the word, least significant first; a parity bit when PARITY_EN is 1 (even parity: the data and parity bits together hold an even number of ones) or 2 (odd parity: an odd number), and none when it is 0; and STOP_BITS stop bits of 1, where STOP_BITS is 1 or 2. Between frames tx is 1.
A cycle with tx_start high and tx_busy low starts a frame of the tx_data present in that cycle, and the start bit begins in the next cycle. tx_busy is high from the first cycle of the start bit to the last cycle of the last stop bit, and tx_start is ignored while it is high.
resetn is a synchronous, active-low reset: it abandons any frame, sets tx to 1 and clears tx_busy.