Fixed Point Multiplier
Medium · Combinational · SystemVerilog · VHDL
Design a signed fixed-point multiplier.
A QM.N fixed-point number is an M+N-bit two's-complement integer read with the binary point N bits from the right: a bit pattern x stands for x · 2^-N, the top M bits are the integer part with the sign, and the low N bits are the fraction. The arithmetic is plain integer arithmetic with the binary point kept by convention, which is why signal-processing and machine-learning hardware uses fixed point where floating point costs too much.
a, b and result are QM.N values. result is the exact product of a and b rounded to a multiple of 2^-N: toward -∞ when round is 0, and to the nearest multiple, ties toward +∞, when round is 1. It holds the low M+N bits of that value, so when the value does not fit in QM.N it has wrapped.
overflow is 1 when the exact product does not fit in QM.N. Rounding plays no part in it, so a product that fits but rounds up out of range wraps result with overflow 0.
The module is combinational.