LFSR Pseudo-Random Number Generator
Medium · Sequential · SystemVerilog
Implement a Fibonacci LFSR (Linear Feedback Shift Register) pseudo-random number generator that shifts right on each enabled clock cycle, producing a maximal-length pseudo-random sequence.
## Background
A Linear Feedback Shift Register is a shift register whose input bit is computed as the XOR of selected bits (called taps) of the register's current state. LFSRs are widely used for pseudo-random number generation, scrambling, and error detection because they produce long, statistically uniform sequences using minimal logic.
This module uses the **Fibonacci** form with a **right-shift** structure:
- The feedback bit is computed as the XOR of all state bits at positions where {TAPS}[i] = 1. - On each enabled clock edge, all bits shift right by one position, and the feedback bit is inserted at the MSB (position $WIDTH - 1$). - {prng_out} exposes the **current state before the shift** occurs on that clock edge.
Formally: $feedback = XOR_{i} (state[i] \text{ where } TAPS[i] = 1)$, and $next\_state = \{feedback, state[WIDTH-1:1]\}$.