Floating Point Multiplier
Hard · Combinational · SystemVerilog · VHDL
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Design a combinational module that multiplies two IEEE 754 single-precision (32-bit) floating-point numbers a and b and produces their product result, along with overflow and underflow status flags.
Each 32-bit value is laid out as: bit 31 is the sign, bits 30–23 are the 8-bit biased exponent (bias = 127), and bits 22–0 are the 23-bit mantissa fraction. A normal number has an implicit leading 1 prepended to the fraction, giving a 24-bit significand 1.mantissa.
Special-value rules (evaluated in priority order before the general algorithm):
1. If either a or b is NaN (exponent = 255 and mantissa ≠ 0), result must be the canonical quiet NaN 32'h7FC00000; overflow and underflow are both 0. 2. If one input is infinity (exponent = 255, mantissa = 0) and the other is zero (exponent = 0, mantissa = 0), the result is an invalid operation: result = 32'h7FC00000 (quiet NaN); overflow = 0, underflow = 0. 3. If either input is ±∞ (exponent = 255, mantissa = 0, after ruling out case 2 above), result = {sign_a ⊕ sign_b, 8'd255, 23'd0} (signed infinity); overflow = 1, underflow = 0. 4. If either input is ± 0 (exponent = 0, mantissa = 0), result = signed zero with sign = sign_a ⊕ sign_b, exponent = 0, mantissa = 0; overflow = 0, underflow = 0. 5. Otherwise both inputs are finite non-zero normals — apply the multiplication algorithm below.
Multiplication algorithm (normal × normal):
1. Sign: sign = sign_a ⊕ sign_b. 2. Exponent sum: exp_sum = exp_a + exp_b - 127 (remove one bias from the double-biased sum). 3. Significand product: Prepend the implicit leading 1 to each 23-bit mantissa to form two 24-bit significands. Compute their 48-bit product: full_product[47:0] = {1, mantissa_a} × {1, mantissa_b}. 4. Normalize: The product is in the range [1, 4). If bit 47 of full_product is set (product ≥ 2.0), shift right by 1 and increment exp_sum by 1. After normalization the leading 1 occupies bit 46; the 23-bit result mantissa is full_product[46:24]. 5. Round to nearest, ties to even: Use full_product[23] as the guard bit and the OR of full_product[22:0] as the sticky bit. Round up if (guard = 1 and sticky = 1) or (guard = 1 and sticky = 0 and result mantissa LSB = 1). 6. Overflow check: If exp_sum ≥ 255 after normalization and rounding, set overflow = 1, underflow = 0, and result = {sign, 8'hFF, 23'd0} (signed infinity). 7. Underflow check: If exp_sum ≤ 0 after normalization (flush-to-zero; subnormal results are not required), set underflow = 1, overflow = 0, and result = signed zero {sign, 8'd0, 23'd0}. 8. Normal result: result = {sign, exp_sum[7:0], mantissa_23bits}; overflow = 0, underflow = 0.
Notes:
- Denormalized (subnormal) inputs (exponent = 0, mantissa ≠ 0) need not be handled correctly; the testbench does not exercise them. - The module is purely combinational — no clocks or resets. - overflow and underflow are never both asserted simultaneously.