Stopwatch
Medium · Sequential · SystemVerilog
Design a stopwatch that counts hours, minutes, and seconds.
{Secs} increments on each rising edge of {CLK} and wraps from $59$ to $0$. {Mins} increments each time {Secs} wraps, itself wrapping from $59$ to $0$. {Hours} increments each time {Mins} and {Secs} wrap together, counting $0$ to $23$.
When {RST} is asserted, all outputs reset to $0$ asynchronously.