Stopwatch
Easy · Sequential · SystemVerilog · VHDL
Design a stopwatch that counts hours, minutes, and seconds.
secs increments every cycle and wraps from 59 to 0. mins increments each time secs wraps and itself wraps from 59 to 0. hours increments each time mins wraps and wraps from 23 to 0.
rst is an asynchronous, active-high reset that sets all three counts to 0.