Divisible by 3
Easy · Sequential · SystemVerilog · VHDL
Design a serial checker for divisibility by three.
The bits of an unsigned number of any length arrive on din, one per cycle, most-significant bit first. dout is 1 when the number formed by the bits received since reset is divisible by three, and 0 otherwise; a bit is included from the cycle after it is on din. Before any bit has been received dout is 0.
resetn is a synchronous, active-low reset; it discards the bits received so far and holds dout at 0. A bit on din during reset is not received.