Skid Buffer
Medium · Sequential · SystemVerilog
Design a valid/ready elastic buffer with exactly one slot of skid storage that decouples the upstream and downstream ready timing paths.
The module uses AXI-stream-style handshaking on both ports. A transaction occurs on a port when both its valid and ready signals are asserted on the same rising clock edge: - Input transaction: {s_valid} $= 1$ AND {s_ready} $= 1$ - Output transaction: {m_valid} $= 1$ AND {m_ready} $= 1$
**Pass-through operation:** When the skid slot is empty and {m_ready} $= 1$, incoming data passes directly to the output. If {s_valid} $= 1$, then {m_valid} $= 1$, {m_data} $=$ {s_data}, and {s_ready} $= 1$. No data is stored internally; the transaction completes in one cycle.
**Backpressure capture:** When {m_ready} $= 0$ and an input transaction completes ({s_valid} $= 1$ AND {s_ready} $= 1$), the incoming data is written into the skid slot. On the following clock edge {s_ready} deasserts because the skid slot is now occupied.
**Full slot:** When the skid slot holds data ({s_ready} $= 0$), {m_valid} $= 1$ and {m_data} is driven from the skid slot contents. Once {m_ready} $= 1$, the output transaction completes, the skid slot is cleared, and {s_ready} reasserts on the next clock edge.
**Registered ready:** {s_ready} must be a registered output — it must not be combinationally dependent on {m_ready}. This breaks the ready timing arc and prevents combinational paths from the downstream consumer back to the upstream producer.