Vector Sort
Hard · Sequential · SystemVerilog · VHDL
Design a sorter that holds eight unsigned BITWIDTH-bit words and outputs them sorted.
Each cycle with sortit low loads din: the module stores the last eight words loaded, 0 for any not yet loaded since reset. A cycle with sortit high loads nothing.
dout is registered. In the cycle after a cycle with sortit high, it holds the eight stored words sorted, the largest in the least significant BITWIDTH bits and each more significant chunk holding the next smaller word, so the smallest is in the most significant chunk. In the cycle after a cycle with sortit low, dout is 0.
resetn is a synchronous, active-low reset that sets dout and every stored word to 0.