Clock Divider
Easy · Sequential · SystemVerilog · VHDL
Design a clock divider that produces div2, div4 and div6, clocks with 2, 4 and 6 times the period of clk and a 50% duty cycle.
Number the cycles from 0, the first cycle after reset. In cycle k, div2 is high when k mod 2 = 1, div4 is high when k mod 4 is 1 or 2, and div6 is high when k mod 6 is 1, 2 or 3.
resetn is a synchronous, active-low reset; it holds all three outputs low, and the numbering restarts from 0 when it is released.