Synchronous FIFO
Medium · Sequential · SystemVerilog
Design a synchronous first-in-first-out (FIFO) buffer that stores up to DEPTH entries of DATA_WIDTH bits each, operating in a single clock domain.
The FIFO has a write port and a read port controlled by {wr_en} and {rd_en}. On each rising clock edge:
- If {wr_en} is asserted and the FIFO is not full, {wr_data} is written to the tail of the FIFO and the write pointer advances. - If {rd_en} is asserted and the FIFO is not empty, the entry at the head of the FIFO is captured into {rd_data} and the read pointer advances. - If both {wr_en} and {rd_en} are asserted simultaneously and the FIFO is neither full nor empty, both the write and read operations complete in the same clock cycle, leaving {count} unchanged. - If {wr_en} is asserted but the FIFO is full, the write is silently discarded — no data is corrupted and the write pointer does not advance. - If {rd_en} is asserted but the FIFO is empty, the read is a no-op — {rd_data} holds its last valid value and the read pointer does not advance.
{full} asserts when {count} $=$ DEPTH. {empty} asserts when {count} $=$ 0.
{count} reflects the number of valid entries currently stored in the FIFO. It increments on a write-only cycle, decrements on a read-only cycle, and remains unchanged on a simultaneous read+write cycle or when operations are blocked by full/empty conditions.
{resetn} is a synchronous active-low reset. When {resetn} is low, all internal pointers reset to 0, {count} resets to 0, and {rd_data} resets to 0. After reset, {empty} is asserted and {full} is deasserted.