Synchronous FIFO
Medium · Sequential · SystemVerilog
Design a synchronous FIFO storing up to {DEPTH} words of {DATA_WIDTH} bits.
On each rising edge: a write ({wr_en} high, not {full}) stores {wr_data} at the tail; a read ({rd_en} high, not {empty}) captures the head word into {rd_data}. A simultaneous read and write both complete, leaving {count} unchanged. Blocked operations are no-ops: a write while {full} is discarded, and a read while {empty} holds {rd_data} at its last value.
{full} is high when {count} $=$ {DEPTH}; {empty} when {count} $=$ 0; {count} tracks the number of stored words.
On reset ({resetn} low, synchronous), the pointers, {count}, and {rd_data} clear to $0$, leaving {empty} asserted.