Booth Radix-2 Multiplier
Hard · Sequential · SystemVerilog
Implement a Booth Radix-2 iterative multiplier that computes the signed two's complement product of two $N$-bit inputs over $N+1$ clock cycles.
**Handshake protocol**
Assert {start} high for exactly one clock cycle while providing {multiplicand} and {multiplier}. The module latches both operands on that cycle, begins the Booth algorithm, and holds {valid} low throughout the computation. Exactly $N+1$ clock cycles after the {start} pulse, the module asserts {valid} high for exactly one cycle and presents the $2N$-bit signed result on {product}.
If {start} is asserted while a computation is already in progress, it must be ignored — the current computation continues uninterrupted and completes normally.
**Reset**
{resetn} is a synchronous active-low reset. When {resetn} is low on a rising clock edge, any in-progress computation is aborted immediately, {product} is forced to 0, {partial_product} is forced to 0, and {valid} is forced to 0. Normal operation resumes once {resetn} returns high.