Parallel to Serial Converter
Easy · Sequential · SystemVerilog · VHDL
Design a module that takes the input din and shifts its LSB to the output dout one bit at a time.
The module should begin shifting the input’s LSB when the the input enable signal din_en goes high. In other words, the input enable signal going high indicates that this module should start shifting the current input signal from it’s least significant bit, regardless of which bits the module has already shifted.
If all the input’s bits have been shifted so that there are no more bits to shift, the module should output 0.
When resetn is active, the module should treat the input value as 0. Even when reset goes back to being inactive, the input value should still be treated as 0, unless din_en makes the module begin shifting from the input again.