Carry Look-Ahead Adder
Medium · Combinational · SystemVerilog
Design a parameterized N-bit carry look-ahead adder that exposes the full carry-chain intermediate signals as output ports.
{sum} is the N-bit result of {a} $+$ {b} $+$ {cin}, taken modulo $2^N$. {cout} is the carry out of bit $N-1$: it is $1$ when the true arithmetic result of {a} $+$ {b} $+$ {cin} is greater than or equal to $2^N$, and $0$ otherwise. {overflow} detects signed two's-complement overflow.
{gen} is the N-bit vector of bit-level generate signals: $\text{gen}[i] = a[i] \;\&\; b[i]$. Bit $i$ generates a carry when both input bits are 1, regardless of carry-in.
{prop} is the N-bit vector of bit-level propagate signals:
$\text{prop}[i] = a[i] \oplus b[i]$
Bit $i$ propagates an incoming carry to the next stage when exactly one input bit is 1.