Parameterized PWM Controller with Dead-Time Insertion
Medium · Sequential · SystemVerilog
Design a PWM controller that produces complementary high-side ({pwm_h}) and low-side ({pwm_l}) gate-drive outputs with a programmable dead-time gap between them to prevent shoot-through in half-bridge motor-drive circuits.
The module maintains an internal cycle counter that runs from $0$ to {period}$-1$ and then wraps back to $0$. Each time the counter resets to $0$, the current values of {period}, {duty}, and {dead_time} are latched into internal registers; changes to these inputs during a period take effect only at the next period boundary.
**Fault detection.** Before generating any output, the controller checks whether {duty}$+${dead_time}$\geq${period}. If so, {fault} is asserted and both {pwm_h} and {pwm_l} are forced to $0$ for the remainder of that period. The fault condition is re-evaluated at each period boundary using the newly latched parameters.
**PWM waveform (no fault).** Let the counter value be $c$ and the latched parameters be $P$ ({period}), $D$ ({duty}), and $T$ ({dead_time}):
- {pwm_h} is asserted ($= 1$) when $c < D$ and $D > 0$. - {pwm_l} is asserted ($= 1$) when $c \geq D + T$ and $c < P - T$.
This creates four phases per period: