Round-Robin Arbiter
Medium · Sequential · SystemVerilog
Design a parameterized round-robin arbiter that grants access to one of N requesters per cycle in a fair, rotating order.
The module has N requesters, controlled by the parameter N (default $N = 4$). Each requester signals its need by asserting the corresponding bit of {req}: {req}[i] $= 1$ means requester $i$ is requesting access.
Each cycle, the arbiter scans from the current priority pointer position and grants access to the first requester found (wrapping around). When a grant is issued, {grant} is driven as a one-hot vector with {grant}[i] $= 1$ for the winning requester, and {valid} is asserted. The priority pointer advances past the granted requester on the next cycle, ensuring no single requester can monopolize the bus.
When {req} $= 0$ (no requesters active), {grant} is driven to $0$, {valid} is deasserted, and the priority pointer does not advance.
If a requester deasserts its {req} on the same cycle its grant arrives, the pointer still advances past it on the next cycle.
On the rising edge of {clk}, if {resetn} is low (synchronous active-low reset), the priority pointer resets to $0$, {grant} is cleared to $0$, and {valid} is deasserted.