Register File
Easy · Sequential · SystemVerilog · VHDL
Design an 8-entry register file of 8-bit words with a single port shared by reads and writes.
wr is a synchronous write of din into entry addr, and rd is a synchronous read of entry addr. A read and a write in the same cycle is invalid, and nothing is stored. dout and error are registered and show the outcome of the previous cycle: dout is the word read, or 0 when that cycle was not a valid read, and error is 1 only after an invalid cycle.
resetn is a synchronous, active-low reset; it clears every entry, dout and error to 0.