UART Receiver
Medium · Sequential · SystemVerilog
Design a UART receiver that deserializes the asynchronous serial stream on {rx}, pulsing {rx_valid} for one cycle when a valid frame arrives.
The bit period is $\lfloor$ {CLK_FREQ} $/$ {BAUD_RATE} $\rfloor$ clock cycles (434 at the defaults). A frame is a low start bit, {DATA_BITS} data bits LSB-first, then a high stop bit; {rx} idles high.
On a falling edge while idle, the receiver waits half a bit period and re-samples {rx}: if it is back high, the glitch is ignored; otherwise reception proceeds, sampling each subsequent bit one full bit period after the last — always at bit centers. A stop bit sampled high pulses {rx_valid} with the assembled word on {rx_data}; a stop bit sampled low pulses {frame_error} instead (never both). Either way the receiver returns to idle immediately, ready for the next start bit.
On reset ({resetn} low, synchronous), all outputs clear and the receiver idles.