UART Receiver
Medium · Sequential · SystemVerilog
Design a UART receiver that deserializes an asynchronous serial bitstream on {rx} into parallel data on {rx_data}, asserting {rx_valid} for one cycle when a complete valid frame has been received.
## Baud Rate Generation
The bit period is $\text{CLKS\_PER\_BIT} = \lfloor \text{CLK\_FREQ} / \text{BAUD\_RATE} \rfloor$ clock cycles (integer division). For the default parameters (CLK_FREQ $= 50\,000\,000$, BAUD_RATE $= 115\,200$), CLKS_PER_BIT $= 434$.
## Frame Format
The {rx} line idles high ($1$). A complete received frame consists of:
1. **Start bit** — {rx} goes low ($0$) for one bit period 2. **Data bits** — {DATA_BITS} data bits, LSB first, each lasting one bit period 3. **Stop bit** — {rx} returns high ($1$) for one bit period