Binary to BCD Converter (Double Dabble)
Medium · Sequential · SystemVerilog
Design a sequential module that converts a DATA_WIDTH-bit unsigned binary number to its Binary Coded Decimal (BCD) representation using the Double Dabble shift-and-add-3 algorithm.
Conversion is triggered by asserting {start} for one clock cycle. When {start} is seen, the module latches {binary_in} and begins the Double Dabble algorithm: over DATA_WIDTH consecutive clock cycles it iteratively shifts the combined BCD/binary shift register left by one bit, adding 3 to any 4-bit BCD nibble whose value is $\geq 5$ before each shift. After DATA_WIDTH cycles the three BCD digits are fully computed and written to {bcd_out}, and {done} is asserted for exactly one clock cycle.
The BCD output is a 12-bit value encoding three decimal digits: {bcd_out}[11:8] holds the hundreds digit, {bcd_out}[7:4] holds the tens digit, and {bcd_out}[3:0] holds the ones digit.
If {start} is asserted while a conversion is already in progress, the current conversion is abandoned and a fresh conversion begins immediately from the new {binary_in} value.
{resetn} is a synchronous active-low reset. When {resetn} is low on the rising clock edge, {done} is cleared to 0, {bcd_out} is cleared to 0, and all internal state is reset. No conversion begins until {start} is asserted after reset.