Binary to BCD Converter (Double Dabble)
Medium · Sequential · SystemVerilog
Design a sequential module that converts an unsigned binary number to its Binary Coded Decimal (BCD) representation.
Conversion is triggered by asserting {start} for one clock cycle. After DATA_WIDTH cycles the three BCD digits are written to {bcd_out}, and {done} is asserted for exactly one clock cycle. {bcd_out} is valid only when {done} is high; at all other times its value is undefined.
The BCD output is a 12-bit value encoding three decimal digits: {bcd_out}[11:8] holds the hundreds digit, {bcd_out}[7:4] holds the tens digit, and {bcd_out}[3:0] holds the ones digit.
If {start} is asserted while a conversion is already in progress, the current conversion is abandoned and a fresh conversion begins immediately from the new {binary_in} value.
On reset, {done} is cleared to 0 and any conversion in progress is abandoned.
*Hint: check out the Double Dabble shift-and-add-3 algorithm.*