MIPS ALU
Medium · Combinational · SystemVerilog · VHDL
Design a 32-bit MIPS ALU.
aluc selects the operation, and r is its result:
| aluc | Operation | r |
| 6'b100000 | ADD | low 32 bits of a + b |
| 6'b100001 | ADDU | low 32 bits of a + b |
| 6'b100010 | SUB | low 32 bits of a - b |
| 6'b100011 | SUBU | low 32 bits of a - b |
| 6'b100100 | AND | bitwise AND of a and b |
| 6'b100101 | OR | bitwise OR of a and b |
| 6'b100110 | XOR | bitwise XOR of a and b |
| 6'b100111 | NOR | bitwise NOR of a and b |
| 6'b101010 | SLT | 1 if a is less than b read as two's-complement, else 0 |
| 6'b101011 | SLTU | 1 if a is less than b read as unsigned, else 0 |
| 6'b000000 | SLL | b shifted left by a |
| 6'b000010 | SRL | b shifted right by a, filling with 0s |
| 6'b000011 | SRA | b shifted right by a, filling with copies of its sign bit |
| 6'b000100 | SLLV | b shifted left by a[4:0] |
| 6'b000110 | SRLV | b shifted right by a[4:0], filling with 0s |
| 6'b000111 | SRAV | b shifted right by a[4:0], filling with copies of its sign bit |
| 6'b001111 | LUI | a[15:0] in the upper half, 0s in the lower half |
Any other aluc gives r = 0.
zero is high when r is 0, and negative is r[31], for every operation. carry is the carry out of a + b for ADD and ADDU and the borrow of a - b (high when a is less than b read as unsigned) for SUB and SUBU. overflow is high when, for ADD or SUB with a and b read as two's-complement, the true result does not fit in 32 bits. flag is high when SLT or SLTU finds a less than b. Each of carry, overflow and flag is 0 for every operation not named with it.
The module is combinational.