MIPS ALU
Medium · Combinational · SystemVerilog
Design a 32-bit MIPS ALU. Given operands {a} and {b} and a 6-bit operation select code {aluc}, the ALU produces result {r} and the status output {zero}.
The supported operations are:
| aluc | OP | Behavior | |:------:|:----:|----------| | 6'b100000 | ADD | {r} = {a} + {b} (signed) | | 6'b100001 | ADDU | {r} = {a} + {b} (unsigned) | | 6'b100010 | SUB | {r} = {a} - {b} (signed) | | 6'b100011 | SUBU | {r} = {a} - {b} (unsigned) | | 6'b100100 | AND | {r} = {a} & {b} | | 6'b100101 | OR | {r} = {a} \| {b} | | 6'b100110 | XOR | {r} = {a} ⊕ {b} | | 6'b100111 | NOR | {r} = ~({a} \| {b}) | | 6'b101010 | SLT | {r} = 1 if {a} $<$ {b} (signed), else 0; also sets {flag} | | 6'b101011 | SLTU | {r} = 1 if {a} $<$ {b} (unsigned), else 0; also sets {flag} | | 6'b000000 | SLL | {r} = {b} << {a} | | 6'b000010 | SRL | {r} = {b} >> {a} (logical) | | 6'b000011 | SRA | {r} = {b} >>> {a} (arithmetic) | | 6'b000100 | SLLV | {r} = {b} << {a}[4:0] | | 6'b000110 | SRLV | {r} = {b} >> {a}[4:0] (logical) | | 6'b000111 | SRAV | {r} = {b} >>> {a}[4:0] (arithmetic) | | 6'b001111 | LUI | {r} = {a}[15:0], 16'h0000 |
For any unrecognized {aluc} value, {r} is high-impedance.
{zero} is asserted when {r} equals $0$.
{flag} reflects the comparison result for SLT ({a} $<$ {b} signed) and SLTU ({a} $<$ {b} unsigned); it is high-impedance for all other operations. {carry}, {negative}, and {overflow} are always high-impedance.