Non-Restoring Integer Divider
Medium · Sequential · SystemVerilog
Implement a non-restoring unsigned integer divider that computes the quotient and remainder of two $N$-bit inputs over $N$ clock cycles using an iterative shift-and-add/subtract algorithm.
**Handshake protocol**
Assert {start} high for exactly one clock cycle while providing {dividend} and {divisor}. The module latches both operands on that cycle, begins the non-restoring algorithm, and holds {done} low throughout the computation. Exactly $N$ clock cycles after the {start} pulse, the module asserts {done} high for exactly one cycle and presents the results on {quotient} and {remainder}.
If {start} is asserted while a computation is already in progress, it must be ignored — the current computation continues uninterrupted and completes normally.
**Reset**
{resetn} is a synchronous active-low reset. When {resetn} is low on a rising clock edge, any in-progress computation is aborted immediately, {quotient} is forced to 0, {remainder} is forced to 0, {done} is forced to 0, and {div_by_zero} is forced to 0. Normal operation resumes once {resetn} returns high.