SPI Master
Medium · Sequential · SystemVerilog
Design a synchronous SPI Mode-0 master that performs a full-duplex 8-bit transfer: shifting {tx_data} out on {mosi} while simultaneously capturing 8 bits from {miso} into {rx_data}, with clock and chip-select generation.
## Protocol
SPI Mode 0 (CPOL $= 0$, CPHA $= 0$): {sclk} idles low. Each bit of {tx_data} is driven onto {mosi} before the rising edge of {sclk} so that the slave can sample it on the rising edge. {miso} is sampled on each rising edge of {sclk}. Data is transferred MSB-first: bit $7$ of {tx_data} is driven first, and bit $7$ of {rx_data} holds the first bit captured from {miso}.
## Transfer Sequence
A transfer begins on the clock cycle when {start} $= 1$ and no transfer is currently in progress. {start} asserted while a transfer is in progress is ignored — the ongoing transfer completes unaffected.
When a transfer begins, {cs_n} is driven low and {mosi} is driven with bit $7$ of the latched {tx_data} on that same cycle. The controller then generates 8 complete {sclk} pulses (each pulse is one cycle low followed by one cycle high), sampling {miso} on each rising edge and shifting the captured bits into {rx_data}. After all 8 bits have been transferred, {done} is asserted high for exactly one clock cycle. On the cycle following {done}, {cs_n} is deasserted (driven high) and {sclk} returns low.