AXI4-Lite Slave Register File
Hard · Sequential · SystemVerilog
Design an AXI4-Lite subordinate (slave) controller that exposes a small register file over the AXI4-Lite bus.
## AXI4-Lite Overview
AXI4-Lite defines five independent channels: Write Address (AW), Write Data (W), Write Response (B), Read Address (AR), and Read Data (R). Every channel uses a VALID/READY handshake: a transfer occurs on the rising edge of {clk} when both VALID and READY are asserted simultaneously. The VALID signal is driven by the source; READY is driven by the destination. A source must not wait for READY before asserting VALID, but it must hold VALID and its payload stable until the handshake completes.
## Register File
The register file contains NUM_REGS registers, each DATA_WIDTH bits wide, all initialized to $0$ after reset. Registers are byte-addressed: register index $i$ occupies byte addresses $i \times (\text{DATA\_WIDTH} / 8)$ through $(i+1) \times (\text{DATA\_WIDTH} / 8) - 1$. A byte address maps to register index $\lfloor \text{addr} \div (\text{DATA\_WIDTH} / 8) \rfloor$. An address is in-range if the computed index is less than NUM_REGS; otherwise it is out-of-range.
## Write Transaction