Fixed Point Adder
Easy · Combinational · SystemVerilog · VHDL
Design a parameterized fixed-point adder for sign-magnitude operands.
a, b and c are N-bit sign-magnitude values: bit N-1 is the sign (1 for negative) and the low N-1 bits are the magnitude. Q is the number of fractional bits; both operands share it, so it does not change the addition.
When a and b have the same sign, c has that sign and its magnitude is the low N-1 bits of the sum of the two magnitudes, so a sum that does not fit wraps. When the signs differ, the magnitude of c is the difference of the two magnitudes and its sign is that of the operand with the larger magnitude; equal magnitudes give +0.
The module is combinational.