Fixed Point Adder
Easy · Combinational · SystemVerilog
Implement a parameterized fixed-point adder in sign-magnitude representation. Each operand is {N} bits: bit [N-1] is the sign and bits [N-2:0] hold the magnitude. The parameter {Q} names the fractional-bit count of the fixed-point format.
The output {c} is computed as follows:
- **Same sign**: add the magnitudes and keep the common sign (magnitude overflow beyond the $N-1$ magnitude bits is not handled). - **Different signs**: subtract the smaller magnitude from the larger; the sign follows the operand with the larger magnitude. Equal magnitudes produce $+0$ (sign bit $0$).