Pipelined Multiply-Accumulate (MAC) Unit
Hard · Sequential · SystemVerilog
Implement a 2-stage pipelined multiply-accumulate (MAC) unit that multiplies two unsigned operands and adds each product to a running accumulator, with configurable accumulator width and an optional per-sample clear.
**Pipeline structure**
The module has two pipeline stages:
- **Stage 1 (multiply):** On each rising clock edge, {A}, {B}, {valid_in}, and {accum_clr} are registered. The product $A \times B$ is computed and stored as an internal register `product_stage`. {valid_in} is registered as `valid_pipe`, and {accum_clr} is registered as `clr_pipe`.
- **Stage 2 (accumulate):** On each rising clock edge, if `valid_pipe` is high, the accumulator {result} is updated: if `clr_pipe` is high, {result} is set to `product_stage` (restart from the new product); if `clr_pipe` is low, `product_stage` is added to the running sum: $result \leftarrow result + product\_stage$. {valid_out} is registered from `valid_pipe`.
**Valid timing**