Serial to Parallel Converter
Easy · Sequential · SystemVerilog · VHDL
Design a serial-to-parallel converter. Each cycle din_valid is high, one bit is accepted from din_serial. After 8 valid bits, the assembled byte appears on dout_parallel — first received bit in the most significant position, last in the least significant — and dout_valid pulses for exactly one cycle.
If din_valid deasserts at any point, the bit counter clears and accumulation restarts with the next valid bit. rst_n is an asynchronous active-low reset that clears all outputs and internal state.