Packet Router
Hard · Sequential · SystemVerilog · VHDL
In some high-speed datapaths, data arrives as a continuous stream without a per-byte ready/valid handshake. The receiving logic still needs to determine where a packet starts, whether its contents were corrupted, which receiver it is intended for, and where it ends. Those decisions must be made while the stream continues to arrive.
Design a serial packet router for this stream. The router finds each packet and checks it for corruption. Then it sends the packet out on one of three links, with a new sender address and a new check byte.
Packet format
A byte arrives on rx_data every cycle. Each packet starts with a preamble of seven 0x55 bytes, followed by a start frame delimiter (SFD), 0xD5. The fields of the packet come directly after the SFD, with no gaps:
''' 55 55 55 55 55 55 55 D5 | TYPE | RECEIVER | SENDER | PAYLOAD | FCS preamble SFD | 1 | 1 | 1 | 1 to 64 | 1 '''
Type
TYPE describes the rest of the packet. The upper 6 bits hold the payload length in bytes, minus one: 0 means 1 byte, and 63 means 64 bytes. The lower 2 bits select how to compute the FCS (see FCS section below).
Receiver
RECEIVER is the address of the packet's destination. If the top four bits match DOMAIN_A, the router sends the packet out on tx_a_data. If they match DOMAIN_B, it sends the packet out on tx_b_data. If they match neither, the packet goes back upstream on tx_up_data.
Sender SENDER is the 8-bit address of the source. The packet router replaces this field with its own LOCAL_ADDR, or 0x00 if the packet is going back upstream.
Payload PAYLOAD is the data, 1 to 64 bytes.
FCS The last byte is the frame check sequence (FCS). Bits can flip on a serial line and corrupt a packet. To find these errors, the sender computes the FCS from the contents of the packet and sends it as the last byte. The receiver computes the FCS again and compares it with the FCS that it received.
The FCS covers the TYPE, RECEIVER, SENDER and payload fields of the packet, in that order. The lower 2 bits of TYPE select the method:
| Lower 2 bits of TYPE | FCS |
| 00 | the CRC-8 of the bytes |
| 01 | the XOR of the bytes (parity) |
| 10 | the sum of the bytes, modulo 256 (checksum) |
| 11 | not used |
The CRC-8 is the standard one with polynomial 0x07 (x^8+x^2+x+1): most significant bit first, no reflection and no final XOR.
How to compute the CRC-8
1. Set the CRC to 0x00. 2. For each byte, XOR the byte into the CRC. Then do this eight times: shift the CRC left by one bit, and if the bit shifted out is 1, XOR the CRC with 0x07. 3. After the last byte, the CRC is the FCS.
If the FCS that a packet arrives with does not match the FCS computed from its contents, the packet is corrupted. The router still sends it, with a correct FCS for its new contents, and the error flag of its link (tx_a_error, tx_b_error or tx_up_error) is high in the cycle that the FCS goes out. A packet that goes upstream only because of its address is not an error.
Timing
The router handles one byte every cycle and never stalls. Each byte of a packet goes out on its link exactly 10 cycles after the router samples it on rx_data. This delay gives the router time to read RECEIVER before the first preamble byte must go out. The preamble of the next packet can start in the cycle right after the FCS. When a link has no packet byte to send, it outputs 0x00.
Reset
resetn is a synchronous, active-low reset. It discards every packet in progress and sets all outputs to zero. Bytes that arrive while resetn is low do not count toward a preamble.