Growing Pulse
Easy · Sequential · SystemVerilog · VHDL
Design a circuit that generates a growing pulse signal. The growing pulse signal has each low/high pair one clock cycle longer than the last:
''' ___ _______ ___________ | | | | | | pulse ____| |_______| |___________| | ...
cycles 1 1 2 2 3 3''' pulse changes at the start of a clock cycle, and the circuit supports intervals up to 2^32-1 cycles; behavior beyond that is unspecified.
resetn is a synchronous, active-low reset that holds pulse low and restarts the pattern from the one-cycle low interval.