Flippy Bits
Easy · Sequential · SystemVerilog · VHDL
Design a circuit that outputs a sequence of flippy bits. A sequence of flippy bits starts as a single 0 and is built by repeatedly appending the complement of everything so far: each 0 becomes 1, each 1 becomes 0, and the bits keep their order. Each step doubles the length:
'''start 0 step 1 0 + 1 = 01 step 2 01 + 10 = 0110 step 3 0110 + 1001 = 01101001 step 4 01101001 + 10010110 = 0110100110010110 ...''' Each cycle, bit_out gives the next bit of the sequence. The circuit supports the first 2^32 bits after each reset; behavior beyond that is unspecified.
resetn is a synchronous, active-low reset that holds bit_out at 0 and restarts the sequence.