UART Transmitter
Hard · Sequential · SystemVerilog
Design a UART transmitter that serializes {tx_data} onto the {tx} line using the standard asynchronous framing: one start bit, {DATA_BITS} data bits (LSB first), an optional parity bit, and {STOP_BITS} stop bit(s).
## Baud Rate Generation
The bit period is $\text{CLKS\_PER\_BIT} = \lfloor \text{CLK\_FREQ} / \text{BAUD\_RATE} \rfloor$ clock cycles (integer division). Each transmitted bit is held on {tx} for exactly CLKS_PER_BIT consecutive clock cycles.
## Frame Format
A complete frame is transmitted in this order:
1. **Start bit** — {tx} driven low ($0$) for one bit period 2. **Data bits** — {DATA_BITS} bits of {tx_data}, transmitted LSB-first, each held for one bit period 3. **Parity bit** (only when {PARITY_EN} $\neq 0$) — even parity ($\text{PARITY\_EN} = 1$): parity bit $=$ XOR of all {DATA_BITS} data bits; odd parity ($\text{PARITY\_EN} = 2$): parity bit $=$ inverted XOR of all data bits; held for one bit period 4. **Stop bit(s)** — {tx} driven high ($1$) for {STOP_BITS} bit periods