Stopwatch
Medium · Sequential · SystemVerilog
Design a stopwatch module that counts hours, minutes, and seconds.
{Secs} counts from $0$ to $59$, incrementing by $1$ on each rising edge of {CLK}. When {Secs} reaches $59$, it wraps to $0$ on the next cycle. {Mins} increments by $1$ each time {Secs} wraps from $59$ to $0$, and itself wraps from $59$ to $0$. {Hours} increments by $1$ each time both {Mins} and {Secs} wrap simultaneously, and counts in a $0$ to $23$ cycle.
When {RST} is asserted (high), all outputs reset to $0$ asynchronously.