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Square Root

Medium · Combinational · SystemVerilog

Write a Verilog module to compute the integer square root of {in_0}, where {in_0} is a signed integer and {out} is a signed integer.

If {in_0} is negative, {out} must be $0$. For non-negative inputs, {out} is the largest integer such that {out}^2 is $\le$ {in_0}.

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