Serial to Parallel Converter
Easy · Sequential · SystemVerilog
Design a serial-to-parallel converter module. The module accepts one bit of input data per cycle on {din_serial} when {din_valid} is high. After receiving $8$ valid bits, the module outputs the assembled byte on {dout_parallel} with the first received bit placed in the most significant bit position and the last received bit in the least significant bit position. {dout_valid} is asserted for exactly one cycle to indicate that {dout_parallel} holds a freshly assembled byte.
If {din_valid} is de-asserted at any point, the bit counter resets to $0$ and accumulation starts over from the next valid bit. The module uses an asynchronous active-low reset ({rst_n}); when reset is de-asserted, all outputs and internal counters are cleared to $0$.