Sequence Detector
Easy · Sequential · SystemVerilog
Design a module that, given a stream of input bits, pulses a $1$ on the output {dout} whenever a $b1010$ sequence is detected on the input {din}.
When the reset-low signal {resetn} goes active, the module should ignore all previously seen bits when searching for $b1010$. If two sequences overlap ($b101010$), {dout} should pulse for both.