Register File
Medium · Sequential · SystemVerilog
Design a simple 1-read/write (1RW) register file (RF) using a multidimensional array of flip-flops in Verilog.
The RF has $8$ entries, each storing one word. The input {din} is written to one of the entries selected by the {addr} when {wr} is asserted. An entry is read by selecting {addr} and asserting {rd}. If a read occurs for an address that has never been written, {dout} and {error} should both be $0$.
Only one operation per clock cycle is allowed: read or write. If {rd} and {wr} are both high in the same cycle, {error} is asserted and {dout} is set to $0$ to indicate an invalid operation.
When {resetn} is low, {dout} and {error} are $0$.