Piso Shift Register
Medium · Sequential · SystemVerilog
Design a module that takes the multi-bit input {din} and shifts the input value’s least significant bit (rightmost bit) to the single-bit output {dout} one bit at a time.
The module should begin shifting the input’s least significant bit when the the input enable signal {din_en} goes high. In other words, the input enable signal going high indicates that this module should start shifting the current input signal from it’s least significant bit, regardless of which bits the module has already shifted.
If all the input’s bits have been shifted so that there are no more bits to shift, the module should output $0$.
When {resetn} is active, the module should treat the input value being shifted as $0$. Even when reset goes back to being inactive, the input value should still be treated as $0$, unless {din_en} makes the module begin shifting from the input again.