Parallel CRC-32
Hard · Combinational · SystemVerilog
Design a purely combinational module that computes the CRC-32/ISO-HDLC checksum update in one cycle: given an input data word {data_in} and the current CRC register state {crc_in}, produce the updated CRC register {crc_out} after processing all {DATA_WIDTH} bits of {data_in}.
## CRC-32/ISO-HDLC Parameters
This module implements the CRC-32 variant used by Ethernet, ZIP, and GZIP:
- Polynomial: $x^{32} + x^{26} + x^{23} + x^{22} + x^{16} + x^{12} + x^{11} + x^{10} + x^{8} + x^{7} + x^{5} + x^{4} + x^{2} + x + 1$ - Reflected polynomial constant: 0xEDB88320 (bit-reversed form of 0x04C11DB7) - Input reflection: bits are processed LSB-first — bit 0 of {data_in} is fed into the LFSR before bit 1, and bit {DATA_WIDTH}$-1$ is fed last - No implicit initial value or final XOR — those are caller responsibilities
## Register and Bit-Update Rule
{crc_in} is the raw CRC register state. The caller is responsible for initializing it to 0xFFFFFFFF before the first data word and XORing {crc_out} with 0xFFFFFFFF to obtain the final CRC-32 checksum after the last word.