MSE Loss
Hard · Sequential · SystemVerilog
Design a module that computes the mean squared error (MSE) between two 4-element signed integer vectors.
The MSE is defined as the average of the four squared element-wise differences:
MSE = $\frac\{\($ {in_0_0} $-$ {in_1_0} $)^2 + ($ {in_0_1} $-$ {in_1_1} $)^2 + ($ {in_0_2} $-$ {in_1_2} $)^2 + ($ {in_0_3} $-$ {in_1_3} $)^2}{4}$
The result is registered: {out} updates on the rising edge of {clk} only when {enable} is asserted. When {rst_n} is de-asserted (low), {out} resets asynchronously to $0$.
{out} is a 32-bit sign-extended representation of the 8-bit MSE result.