MIPS ALU
Medium · Combinational · SystemVerilog
Design a 32-bit MIPS ALU. Given operands {a} and {b} and a 6-bit operation select code {aluc}, the ALU produces result {r} and the status output {zero}.
The supported operations are:
'''aluc OP Behavior 100000 ADD r = a + b (signed) 100001 ADDU r = a + b (unsigned) 100010 SUB r = a - b (signed) 100011 SUBU r = a - b (unsigned) 100100 AND r = a & b 100101 OR r = a | b 100110 XOR r = a ⊕ b 100111 NOR r = ~(a | b) 101010 SLT r = 1 if a < b (signed), else 0; also sets flag 101011 SLTU r = 1 if a < b (unsigned), else 0; also sets flag 000000 SLL r = b << a 000010 SRL r = b >> a (logical) 000011 SRA r = b >>> a (arithmetic) 000100 SLLV r = b << a[4:0] 000110 SRLV r = b >> a[4:0] (logical) 000111 SRAV r = b >>> a[4:0] (arithmetic) 001111 LUI r = a[15:0], 16'h0000''' For any unrecognized {aluc} value, {r} is high-impedance.
{zero} is asserted when {r} equals $0$.
{flag} reflects the comparison result for SLT ({a} $<$ {b} signed) and SLTU ({a} $<$ {b} unsigned); it is high-impedance for all other operations. {carry}, {negative}, and {overflow} are always high-impedance.