Maximum Finder
Medium · Sequential · SystemVerilog
Implement a 2-stage pipelined module that finds the maximum of four unsigned inputs {x0}, {x1}, {x2}, and {x3}.
On each rising edge of {clk}, the first stage computes the max of {x0}/{x1} and {x2}/{x3}. The second stage outputs {max_value} as the max of those two results. When {rst} is asserted, pipeline registers reset to $0$.