Hamming(7,4) Syndrome Decoder with SEC
Hard · Combinational · SystemVerilog
Implement a Hamming(7,4) syndrome decoder that accepts a 7-bit encoded codeword, computes the 3-bit syndrome to detect and correct any single-bit error (SEC), and outputs the corrected 4-bit data along with status flags.
## Bit Layout
A Hamming(7,4) codeword stores 4 data bits in 7 bit positions (1-indexed):
| Position | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |----------|-----|-----|-----|-----|-----|-----|-----| | Bit type | p1 | p2 | d1 | p4 | d2 | d3 | d4 | | Port index | [0] | [1] | [2] | [3] | [4] | [5] | [6] |
So {codeword_in}[0] = p1, [1] = p2, [2] = d1, [3] = p4, [4] = d2, [5] = d3, [6] = d4.
The data output {data_out} is assembled as $\{d4, d3, d2, d1\}$ = {corrected[6], corrected[5], corrected[4], corrected[2]}.