Gradient Descent
Hard · Sequential · SystemVerilog
Design a module that performs one step of gradient descent weight update.
On each rising edge of {clk}, if {rst} is asserted, {updated_weight} resets to $0$. Otherwise, if {enable} is asserted, {updated_weight} is updated according to:
${updated\_weight} = {current\_weight} - \left(\frac{{gradient} \times {learning\_rate}}{2^{FRAC\_BITS}}\right)$
The product of {gradient} and {learning\_rate} is computed as a $(DATA\_WIDTH + LR\_WIDTH)$-bit signed value, then arithmetically right-shifted by {FRAC\_BITS} bits to produce the scaled update. The result is truncated to {DATA\_WIDTH} bits before being subtracted from {current\_weight}. If {enable} is not asserted, {updated\_weight} holds its previous value.