Fractional Frequency Divider
Easy · Sequential · SystemVerilog
Design a fractional frequency divider that produces {clk_div} at exactly $ 1 / ( $ {MUL2_DIV_CLK} $ / 2) $ of the {clk} frequency.
The module uses a double-edge clocking technique to achieve half-integer division. An internal counter cycles through {MUL2_DIV_CLK} source clock periods. Two intermediate clock signals are generated: one sampled on the rising edge of {clk} and one sampled on the falling edge of {clk}. These are phase-offset by half a clock period and then OR-ed together to produce {clk_div} with a uniform period.
When {rst_n} is de-asserted (low), all internal registers reset to $ 0 $ asynchronously.