IEEE 754 to Q16.16 Fixed-Point Converter
Hard · Combinational · SystemVerilog
Design a combinational module that converts a 32-bit IEEE 754 single-precision floating-point value {float_in} into a 32-bit signed Q16.16 fixed-point value {fixed_out}, asserting {overflow} when the value exceeds the representable range, and asserting {nan_flag} when the input is a NaN.
**IEEE 754 structure:** {float_in} is laid out as $\{sign[31],\ exp[30:23],\ mantissa[22:0]\}$. For normal numbers (exp $\neq$ 0 and exp $\neq$ 255), the value is $(-1)^{sign} \times 1.mantissa \times 2^{exp-127}$.
**Q16.16 format:** {fixed_out} is a 32-bit two's complement number with 16 integer bits (bits [31:16]) and 16 fractional bits (bits [15:0]). The representable range is approximately $\pm 32767.99998$ with resolution $2^{-16}$. Fractional bits beyond the representable precision are truncated (no rounding).
**Conversion:** Let the 24-bit significand $M = \{1, mantissa[22:0]\}$ (implicit leading 1). The Q16.16 integer representation of the magnitude is $M \times 2^{true\_exp - 7}$, where $true\_exp = exp - 127$. Shift $M$ left by $(true\_exp - 7)$ if that quantity is non-negative, or right by $(7 - true\_exp)$ if negative. Apply two's complement negation when $sign = 1$.
**Special cases (must be handled exactly):**
- exp $= 0$: zero or denormal — {fixed_out} $= 0$, {overflow} $= 0$, {nan_flag} $= 0$. - exp $= 255$, mantissa $\neq 0$: NaN — {nan_flag} $= 1$, {fixed_out} $= 0$, {overflow} $= 0$. - exp $= 255$, mantissa $= 0$: Infinity — {overflow} $= 1$, {fixed_out} $= 32