Fixed-Point Multiplier (Q-Format)
Medium · Combinational · SystemVerilog
Design a purely combinational signed fixed-point multiplier in Q-format (QM.N) that multiplies two signed inputs and returns a result in the same format, with optional round-to-nearest and overflow detection.
The module is parameterized by INT_BITS ($M$) and FRAC_BITS ($N$), giving a total word width of $W = M + N$ bits. Both {a} and {b} are signed two's-complement values in QM.N format: the binary point is placed $N$ bits from the LSB, so the value of a bit vector $x$ is $x \cdot 2^{-N}$.
**Full product computation.** Multiply {a} and {b} as signed $W$-bit integers to produce a $2W$-bit signed full product. This full product has $2N$ fractional bits and $2M$ integer bits (including two sign bits due to sign-extension).
**Result extraction.** The Q-format result is obtained by discarding the $N$ LSBs (low fractional guard bits) and the top $W+1$ bits (the redundant sign extension), keeping bits $[2W-N-2 : N-1]$ of the full product as the $W$-bit output {result}. With the default parameters $W = 8$, $N = 4$, this means bits $[14:7]$ of the 16-bit full product.
**Rounding.** When {round} $= 1$ and bit $[N-1]$ of the full product (the guard bit, bit $[3]$ for $N = 4$) is $1$, add $1$ to the extracted $W$-bit result before presenting it on {result}. When {round} $= 0$, truncate: use the extracted result as-is.
**Overflow detection.** Assert {overflow} $= 1$ when the true product cannot be represented in QM.N format. This occurs when the top $M+1$ bits of the full product — bits $[2W-1 : W-1]$ — are not all equal (not all $0$ or all $1$). When overflow is detected, {result} reflects the extracted (and optionally rounded) bits regardless; the caller is responsible for handling it.