Fixed Point Adder
Easy · Combinational · SystemVerilog
Implement a parameterized fixed-point adder that operates in sign-magnitude representation. Each operand is {N} bits wide: the most significant bit (bit $N-1$) is the sign bit, and bits $N-2:0$ hold the magnitude.
The output {c} is computed as follows:
- **Same sign**: if {a} and {b} have the same sign bit, add their magnitudes and keep the common sign. (Note: magnitude overflow is not handled beyond the $N-1$ magnitude bits.) - **Different signs**: subtract the smaller magnitude from the larger. The sign of the result follows the operand with the larger magnitude. If the magnitudes are equal, the result is $+0$ (sign bit $= 0$).