8b/10b Line Encoder
Hard · Sequential · SystemVerilog
Design a pipelined 8b/10b line encoder that converts each 8-bit input symbol into a 10-bit encoded output while maintaining DC balance through a running disparity register.
The 8b/10b standard splits each 8-bit input into two groups: a 5-bit subgroup {data_in}$[4:0]$ (bits abcde) encoded into 6 bits, and a 3-bit subgroup {data_in}$[7:5]$ (bits fgh) encoded into 4 bits, yielding a 10-bit output {data_out}. Every valid encoded symbol has exactly 4, 5, or 6 ones — never fewer than 4 or more than 6 — ensuring bounded DC offset.
**Running Disparity**
Running disparity (RD) tracks cumulative DC balance across the serial bitstream. RD is either negative (RD−, represented as {rd_out} $= 0$) or positive (RD+, represented as {rd_out} $= 1$). For each encoded symbol, the encoder selects the RD− or RD+ encoding based on the current RD value, then updates RD according to the disparity of the output word:
- If the output word has more ones than zeros (disparity $+2$), RD transitions to RD+. - If the output word has more zeros than ones (disparity $-2$), RD transitions to RD−. - If the output word has equal ones and zeros (disparity $0$, a neutral symbol), RD is unchanged.
**Data Symbols (k_in = 0)**